Wireless, handheld and other battery-powered mobile devices seem ubiquitous in the modern world. Much of the market success enjoyed by these electronic devices is attributable to, among other things, each device's functionality and degree of mobility. While battery-powered devices allow mobile users to operate in all environments and geographical locations, such products are prone to periodic recharging and replacement. In other words, batteries are capable of providing only limited operation time and suffer from a short lifespan. Therefore, systems that extend battery life in mobile devices are demanded by consumers.
As a result of this demand, many mobile devices and other computer systems utilize controlled power supply voltage ramping to dynamically change the power supply voltage of the device according to its operational mode. For instance, as a device enters a low power mode (e.g., stand-by mode), the power supply voltage can be dynamically lowered or ramped down to conserve battery life. Additionally, as a device wakes up from a low power mode and desires normal operation of a device or higher performance, the power supply voltage of the system can be increased, or ramped up, to meet this need. Thus, system efficiency is maximized and battery life is extended to satisfy today's highly mobile consumers.
FIG. 1 illustrates a prior art clock generating circuit 100 having a phase lock loop (“PLL”) capable of adapting to dynamic power supply voltage ramps. As illustrated, the PLL of the clock generating circuit 100 might include a phase frequency detector 102 which receives a reference clock signal 104 and a feedback clock signal 106 and generates a phase adjust signal 118. Traditionally, the reference clock signal 104 is the system clock signal generated from a crystal oscillator (not shown). However, the reference clock signal 104 may be any desired periodic clock signal. A charge pump 108 receives the phase adjust signal 118 and is coupled to both a loop filter 110 and a variable clock signal generator 112. Conventionally, the charge pump 108, generates a charged control signal 122 (i.e., a pumped up or down current) that is passed through a loop filter 110 (or low pass filter). In turn, the loop filter 110 generates a phase compensated control signal 124 (e.g., a DC voltage) that is received by the variable clock signal generator 112. While the variable clock signal generator 112 may include a voltage controlled oscillator, it may also include any oscillator operative to produce a periodic clock signal with a frequency based on one or more characteristics of its input signal. The output of the variable clock signal generator 112 is a generated clock signal 114.
As appreciated by those with ordinary skill in the art, the clock generating circuit 100 uses feedback so that the generated clock signal 114 can “lock onto” a desired frequency based on the frequency of a reference clock signal 104. In FIG. 1, feedback loop L accepts the generated clock signal 114 and generates a feedback clock signal 106 based on the generated clock signal 114. As illustrated, a divider 116 may be employed in the feedback loop L to tune the frequency of the feedback clock signal 106. In some prior art systems, the divider 116 serves to make the frequency of the feedback clock signal 106 a rational or fractional multiple of the frequency of the reference clock signal 104.
During normal operation, the PLL serves to automatically increase or decrease the frequency of the generated clock signal 114 until it matches the frequency of the reference clock signal 104. As the variable clock signal generator 112 generates the generated clock signal 114, the phase frequency detector 102 accepts the feedback clock signal 106, compares the frequency of the feedback clock signal 106 to that of the reference clock signal 104 and causes the charge pump 108 to speed up or slow down the variable clock signal generator 112. For instance, in one embodiment, if the frequency of the generated clock signal 114 falls behind that of the reference clock signal 104, the phase frequency detector 102 will output at least one phase adjust signal 118 causing the charge pump 108 and loop filter 110 to increase the voltage in the phase compensated control signal 124 thereby speeding up the variable clock signal generator 112. Similarly, if the frequency of the generated clock signal 114 creeps ahead of the frequency of the reference clock signal 108, the phase frequency detector 102 will output at least one phase adjust signal 118 causing the charge pump 108 and loop filter 110 to reduce the voltage in the phase compensated control signal 124 thereby slowing down the variable clock signal generator 112.
As one of ordinary skill in the art may appreciate, the prior art clock generating circuit 100 of FIG. 1 can be utilized in prior art systems capable of adapting to dynamic changes in power supply voltage as the operational mode of the system transitions among various states. For instance, power supply voltage (VDD) ramping may occur during a transition from a low power state (e.g., stand-by mode) to a normal power state (e.g., any other normal operation mode), or vice-versa or through more than two states. Utilizing the above general description of the clock generating circuit 100 in connection with the timing diagram of FIG. 14, the performance of the prior art clock generating circuit 100 can be evaluated. The plot of POWER SUPPLY VOLTAGE is measured in volts and indicates the power supply voltage of the clock generating circuit over time. As illustrated for purposes of example, the power supply voltage is constant at VDD1 until it is dynamically ramped down to VDD2. While dynamic power supply voltage ramping can occur linearly as indicated in FIG. 14, it may also take the form of a step-function or may represent any desired change in power supply voltage. The plot shows a transition as the power supply voltage is dynamically ramped from a higher power supply voltage, VDD1, to a lower power supply voltage, VDD2. The plot of PRIOR ART VARIABLE CLOCK SIGNAL GENERATOR INPUT, illustrates the phase compensated control signal 124 in FIG. 1 over time. Lastly, the plot of PRIOR ART FREQUENCY OF GENERATED CLOCK SIGNAL illustrates the frequency of the generated clock signal 114 of FIG. 1 over time.
As indicated by the four labels provided under the time axis in FIG. 14, a dynamic power supply voltage ramping cycle operating with a clock generating circuit may include several modes such as, but not limited to, a clock generating circuit reset mode, a chip reset mode, normal operation mode, power supply voltage (VDD) ramping mode and a post-ramping (return to normal operation) mode. As known in the art, a clock generating circuit reset may be used to temporarily disable or initialize the specific PLL/clock generating circuit as desired. In comparison, a chip reset mode generally occurs upon boot up of the system and initializes the entire integrated circuit upon which the clock generating circuit is typically situated. During both reset modes, the phase frequency detector 108 and loop filter 110 are disabled (i.e., they do not produce an output) and the charge pump 108 opens the feedback loop L. Additionally, as indicated in FIG. 14, the input of the variable clock signal generator 112 has an initial voltage due to the charge stored in the loop filter 110. Therefore, the generated clock signal 114 has a constant frequency. However, as the clock generating circuit 100 is utilized in normal operation, the feedback loop L is closed and the phase frequency detector 102 and the loop filter 110 are enabled (i.e., they produce an output). Consequently, the clock generating circuit 100 requires time for the generated clock signal 114 to effectively “lock onto” the desired frequency of the reference clock signal 104.
When the system undergoes dynamic power supply voltage ramping, the power supply voltage transitions from a first voltage, VDD1, to a second voltage, VDD2, as indicated above. During this stage, FIG. 14 illustrates one example where the variable clock signal generator 112 input voltage exponentially increases over time. Consequently, the frequency of the generated clock signal 114 output from the variable clock signal generator may also exponentially increase in time. After the power supply voltage completes ramping, the generated clock signal 114, now operating at VDD2, must again “re-lock onto” the frequency of the reference clock signal 104. As indicated in the timing diagram, the frequency of the generated clock signal 114 may require a significant amount of time to stabilize.
In summary, the clock generating circuit 100 is compatible with systems employing dynamic power supply voltage ramping. It allows mobile devices to dynamically scale up or down the power supply voltage and conserve power consumption. However, the clock generating circuit 100 suffers from having a frequency-changing generated clock signal 114 during voltage ramping and requires a long resettling time. This phenomenon is attributable to a significant amount of phase error detected at the phase frequency detector 102 and seen at the input of the charge pump 108 during and immediately after power supply voltage ramping.
Therefore, a need exists for faster clock generating circuits such as those adapted for dynamic power supply voltage ramping.